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| * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 1 i. general description the EM78P860 is an 8-bit risc type microprocessor with low power , high speed cmos technology . integrated onto a single chip are on_chip watchdog (wdt) , ram , rom , programmable real time clock /counter , internal interrupt , power down mode , lcd driver and tri-state i/o . the EM78P860 provides a single chip solution to design a message display . ii. features cpu ? operating voltage range : 2.5v~5.5v ? 16kx13 on chip rom ? 2.8kx8 on chip ram ? up to 32 bi-directional tri-state i/o ports ? 8 level stack for subroutine nesting ? 8-bit real time clock/counter (tcc) ? two sets of 8 bit counters can be interrupt sources ? selective signal sources and with overflow interrupt ? programmable free running on chip watchdog timer ? 99.9% single instruction cycle commands ? four modes (internal clock 3.679mhz, external 32.768khz) 1. sleep mode : cpu and 3.679mhz clock turn off, 32.768khz clock turn off 2. idle mode : cpu and 3.679mhz clock turn off, 32.768khz clock turn on 3. green mode : 3.679mhz clock turn off, cpu and 32.768khz clock turn on 4. normal mode : 3.679mhz clock turn on , cpu and 32.768khz clock turn on ? low battery detector ? input port wake up function ? 8 interrupt source , 4 external , 3 internal ? 100 pin qfp (em78860aq, povd disable) (em78860bq, povd enable) or chip (em78860h) ? port key scan function ? port interrupt , pull high and open drain functions ? clock frequency 32.768khz externally lcd ? lcd operation voltage chosen by software ? common driver pins : 16 ? segment driver pins : 60 ? 1/4 bias ? 1/8,1/16 duty iii. application 1. adjunct units
EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 2 iv. pin assignments rom ram cpu input port input port i/o port i/o port lcd output lcd latch & driver clk timing control timer v. functional block diagram seg42 sef43 test seg44/p8.0 seg45/p8.1 seg46/p8.2 seg47/p8.3 seg48/p8.4 seg49/p8.5 seg50/p8.6 seg51/p8.7 seg52/p9.0 seg53/p9.1 seg54/p9.2 seg55/p9.3 seg56/p9.4 seg57/p9.5 seg58/p9.6 seg59/p9.7 vdd1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 gnd nc pllc nc nc nc nc nc xin xout vdd seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 vdd2 seg17 EM78P860 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 com1 com0 seg35 seg34 seg33 seg32 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg41 seg40 seg39 seg38 seg37 seg36 reset p7.7 p7.6 p7.5 p7.4 p7.3/int3 p7.2/int2 p7.1/int1 p7.0/int0 com15/p6.7 com14/p6.6 com13/p6.5 com12/p6.4 com11/p6.3 com10/p6.2 com9/p6.1 com8/p6.0 com7 com6 com5 com4 com3 gnd com2 fig. 1 pin assignments fig. 2 functional block diagram1 * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 3 wdt timer control of sleep and wake-up on i/o ports ioc6 r6 port6 instruction decoder rom interrupt controller r1(tcc) oscillator/timing control prescaler ram r4 instruction register r2 stack xin xout data & control bus 2.5k ram acc r3 r5 alu general ram p60~p67 ioc7 r7 port7 p70~p77 ioc8 r8 port8 p80~p87 ioc9 r9 port9 p90~p97 vi. pin descriptions symbol type function vdd power power gnd power gound xtin i input pin for 32.768 khz oscillator xtout o output pin for 32.768 khz oscillator pllc i phase loop lock capacitor, connect a capacitor 0.01 m to 0.047 m with gnd com0..com7 o common driver pins of lcd drivers com8..com15 o (port6) seg0..seg43 segment driver pins of lcd drivers seg44..seg51 o (port8) seg52..seg59 o (port9) port9 as function key can wake up watchdog. int0 port7(0) port7(0)~port7(3) signal can be interrupt signals. int1 port7(1) int2 port7(2) int3 port7(3) p7.0~p7.7 port7 port 7 can be input or output port each bit. internal pull high function. key scan function. bit6,7 open drain function. p6.0~p6.7 port6 port 6 can be input or output port each bit. and shared with common signal. p8.0~p8.7 port8 port 8 can be input or output port each bit. and shared with common signal. p9.0~p9.7 port9 port 9 can be input or output port each bit. and shared with common signal. test i test pin into test mode , normal low reset i fig. 2 functional block diagram2 EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 4 vii. function description vii.1 operational registers 1. r0 (indirect addressing register) r0 is not a physically implemented register. it is useful as indirect addressing pointer. any instruction using r0 as register actually accesses data pointed by the ram select register (r4). 2. r1 (tcc) ? increased by an internal signal edge applied to tcc , or by the instruction cycle clock. ? written and read by the program as any other register. 3. r2 (program counter) ? the structure is depicted in fig. 4. ? generates 16kx13 on-chip rom addresses to the relative programming instruction codes. ? jmp instruction allows the direct loading of the low 10 program counter bits. ? call instruction loads the low 10 bits of the pc, pc+1, and then push into the stack.. ? ret (retl k, reti) instruction loads the program counter with the contents at the top of stack. ? mov r2,a allows the loading of an address from the a register to the pc, and the ninth and tenth bits are cleared to 0'. ? add r2,a allows a relative address be added to the current pc, and contents of the ninth and tenth bits are cleared to 0'. ? tbl allows a relative address be added to the current pc, and contents of the ninth and tenth bits dont change. ? the most significant bit (a10~a13) will be loaded with the content ofbit ps0~ps3 in the status register (r5) upon the execution of a jmp, call, add r2,a, or mov r2,a instruction. fig. 4 program counter organization pc a13 a12 a11 a10 a9 a8 ret rettl reti call a7~a0 stack 1 stack 2 stack 3 stack 4 stack 5 stack 6 stack 7 stack 8 0000 page0 0000~03ff 0000 page1 0400~07ff 1110 page14 3800~3bff 1111 page15 3c00~3fff 0000 page2 0800~0bff * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 5 event t p remark wdt time out 0 0 sleep mode wdt time out (not sleep mode 0 1 /reset wake up from sleep 1 0 power up 1 1 low pulse on /reset x x x . . don't care r0 r1(tcc) r2(pc) r3(status) r4(rsr) r5(rom page) r6(port6) r7(port7) r8(port8) r9(port9) ra(clk) rb() rc(2.5k ram adress) rd(2.5k ram data) re rf(int flag) 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 : 1f 20 : 3f 16x8 common register ioc6 ioc7 ioc8 ioc9 ioca iocb(lcd address) iocc(lcd data) iocd(pull high) ioce(io, lcd) iocf(int control) rc(address) rd(data) iocb(counter1) iocc(counter2) bank0~bank3 32x8 ~ 32x8 register 0 : 255 band1 256x8 band1 256x8 band10 256x8 page0 page1 . . . . . . . . . . . . . . . . . . . . . . . . address register control register (page0) control register (page1) 4. r3 ( status register ) 7654321 0 - page - t p z dc c ? bit 0 (c) : carry flag ? bit 1 (dc) : auxiliary carry flag ? bit 2 (z) : zero flag ? bit 3 (p) : power down bit. set to 1 during power on or by a wdtc command and reset to 0 by a slep command. ? bit 4 (t) : time-out bit. set to 1 by the slep and wdtc command, or during power up and reset to 0 by wdt time out. ? bit 5 : unused ? bit 6 page : changed iocb~ioce to another page, 0/1 ? page0/page1 ? bit 7 unused fig. 5 data memory configuration EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 6 5. r4 ( ram select register ) ? bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode. ? bit 6 ~ 7 determine which bank is actived among the 4 banks. ? see the configuration of the data memory in fig. 4. 6. r5 ( program page select register) 7654321 0 - - - - ps3 ps2 ps1 ps0 ? bit 0 (ps0) ~ 3 (ps3) page selec bits. page select bits ps3 ps2 ps1 ps0 program memory page (address) 0000 page 0 0001 page 1 0010 page 2 0011 page 3 0100 page 4 0101 page 5 0110 page 6 0111 page 7 1000 page 8 1001 page 9 1010 page 10 1011 page 11 1100 page 12 1101 page 13 1110 page 14 1111 page 15 ? user can use page instruction to change page. to maintain program page by user. otherwise, user can use far jump (fjmp) or far call (fcall) instructions to program user's code. and the program page is maintained by emc's complier. it will change user's program by inserting instruction within program. ? bit4~7 : unused 7. r6 ~r9 ( port 6 ~ port 9) ? five 8-bit i/o registers. 8. ra 7654321 0 idle /358e /lpd /low-bat 0 0 0 0 ? bit0 ~ bit3 unused, please set to "0" * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 7 fig. 6 the relation between /lpd,/povd ? bit6(read/write)(pll enable signal) 0/1=disable/enable the relation between 32.768k and 3.679m can see fig. 7. fig. 7 the relation between 32.768k and 3.679k . ? bit7 idle: sleep mode selection bit 0/1=sleep mode/idle mode. this bit will decide slep instruction which mode to go. these idle mode can be waken up by tcc clock or watch dog or port9 and run from slep next instruction. these sleep mode can be waken up by watch dog or port9 and run from address 00. sleep mode idle mode green mode normal mode ra(7,6)=(0,0) ra(7,6)=(1,0) ra(7,6)=(x,0) ra(7,6)=(x,1) + slep + slep no slep no slep tcc time out x wake-up interrupt interrupt + interrupt + next instruction wdt time out reset wake-up reset reset + next instruction reset reset port9 wake-up reset wake-up + next instruction ? bit4(read only)(low battery signal) 0/1 = battery voltage is low/normal . if the battery voltage is under 3.6v then sends a 0 signal to ra register bit4 or a 1 signal to this bit if vdd is over 3.8v. ? bit5(read/write)(low battery detect enable) 0/1 = low battery detect disable/enable. the relation between /lpd,/povd and /low_bat can see fig 6. vdd vref s2 1 on 0 off s2 1 on 0 off 1 on to low bat to rese t /povd /lpd /lpd + - 1 on 32.768k pll 3.679m /358e switch to system clock 0 1 EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 8 9. rb empty register, please don't use. 10. rc (2.5k ram address)(read/write) 7654321 0 cida7 cida6 cida5 cida4 cida3 cida2 cida1 cida0 ? bit 0 ~ bit 7 select caller id ram address up to 256. 11. rd (2.5k ram address)(read/write) ? bit 0 ~ bit 8 are caller id ram data transfer register. user can see ioca register how to select cid ram banks. 12. re (lcd driver,wdt control)(read/write) 7654321 0 - /wdte /wup9h /wup9l /wuring lcd_c2 lcd_1 lcd_m ? bit0 (lcd_m):lcd_m decides the methods, including duty, bias, and frame frequency. ? bit1~bit2 (lcd_c#):lcd_c# decides the lcd display enable or blanking. change the display duty must set the lcd_c2,lcd_c1 to 00. lcd_c2,lcd_c1 lcd display control lcd_m duty bias 0 0 change duty 0 1/16 1/4 disable(turn off lcd) 1 1/8 1/4 0 1 blanking : : 1 1 lcd display enable : : ? bit3 unused. please set to "0" ? bit4(/wup9l, port9 low nibble wake up enable) : used to enable the wake-up function of low nibble in port9, (1/0=enable/disable) ? bit5 (/wup9h, port9 high nibble wake up enable) : used to enable the wake-up function of high nibble in port9, (1/0=enable/disable) ? bit6 (/wdte, watch dog timer enable) control bit used to enable watchdog timer. (1/0=enable/disable) ? bit7 unused 13. rf (interrupt status register) 7654321 0 int3 - c8_2 c8_1 int2 int1 int0 tcif ? 1 means interrupt request, 0 means non-interrupt ? bit 0 (tcif) tcc timer overflow interrupt flag. set when tcc timer overflows . ? bit 1 (int0) external int0 pin interrupt flag . ? bit 2 (int1) external int1 pin interrupt flag . ? bit 3 (int2) external int2 pin interrupt flag . ? bit 4 (c8_1) internal 8 bit counter interrupt flag . ? bit 5 (c8_2) internal 8 bit counter interrupt flag . * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 9 ? bit 6 :unused. please set to 0. ? bit 7 (int3) external int3 pin interrupt flag. ? high to low edge trigger , refer to the interrupt subsection. ? iocf is the interrupt mask register. user can read and clear. 14. r10~r3f (general purpose register) ? r10~r3f (banks 0~3) all are general purpose registers. vii.2 special purpose registers 1. a (accumulator) ? internal data transfer, or instruction operand holding ? its not an addressable register. 2. cont (control register) 7654321 0 - int ts - pab psr2 psr1 psr0 ? bit 0 (psr0) ~ bit 2 (psr2) tcc/wdt prescaler bits. psr2 psr1 psr0 tcc rate wdt rate 0 0 0 1:2 1:1 0 0 1 1:4 1:2 0 1 0 1:8 1:4 0 1 1 1:16 1:8 1 0 0 1:32 1:16 1 0 1 1:64 1:32 1 1 0 1:128 1:64 1 1 1 1:256 1:128 ? bit 3 ( pab ) : prescaler assignment bit 0/1: tcc/wdt ? bit 4 : unused ? bit 5 ( ts ) : tcc signal source 0 : internal instruction cycle clock 1 : 16.38khz ? bit 6 (int) : int enable flag 0 : interrupt masked by disi or hardware interrupt 1 : interrupt enabled by eni/reti instructions ? bit 7 : unused ? cont register is readable and writable. EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 10 3. ioc6 ~ ioc9 ( i/o port control register ) ? five i/o direction control registers. ? 1 put the relative i/o pin into high impedance, while 0 put the relative i/o pin as output. ? user can see iocb register how to switch to normal i/o port. 4. ioca (ram,io ,page control register)(read/write,initial 00000000) 7654321 0 p8sh p8sl 0 call_4 call_3 call_2 call_1 0 ? bit0 unused ? bit4~bit1: 000" to 1001 are ten blocks of ram area. user can use 2.5k ram with rc ram address. ? bit 5 unused ? bit6: port8 low nibble switch, 0/1= normal i/o port/segment output . ? bit7: port8 high nibble switch , 0/1= normal i/o port/segment output 5. iocb (lcd address) page0 : bit6 ~ bit0 = lcda6 ~ lcda0 the lcd display data is stored in the data ram . the relation of data area and com/seg pin is as below: com15 ~ com8 com7 ~ com0 40h (bit15 ~ bit8) 00h (bit7 ~ bit0) seg0 41h 01h seg1 ::: ::: 7bh 3bh seg59 7ch 3ch empty 7dh 3dh empty 7eh 3eh empty 7fh 3fh empty page1 : 8 bit up-counter (counter1) preset and read out register . ( write = preset ) . after an interruption, it will count from 00. 6. iocc (lcd data) page0 : bit7 ~ bit0 = lcd ram data register page1 : 8 bit up-counter (counter2) preset and read out register. (write=preset) after a interruption, it will count from "00". 7. iocd (pull-high control register) 7654321 0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 ? bit 0 ~ 7 (/ph#) control bit used to enable the pull-high of port7(#) pin. 1: enable internal pull-high 0: disable internal pull-high * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 11 8. ioce (bais, pll control register) page0: 7654321 0 p9sh p9sl p6s bias3 bias2 bias1 0 sc ? bit 0 :sc (scan key signal ) 0/1 = disable/enable. once you enable this bit , all of the lcd signal will have a low pulse during a common period. this pulse has 30us width. please use the procedure to implement the key scan function. a. set port7 as input port b. set iocd page0 port7 pull high c. enable scan key signal d. once push a key . set ra(6)=1 and switch to normal mode. e. blank lcd. disable scan key signal. f. set p6s =0. port6 sent probe signal to port7 and read port7. get the key. g. note!! a probe signal should be delay a instruction at least to another probe signal. h. set p6s =1. port6 as lcd signal. enable lcd. p63 p62 p61 p60 key5 key1 key2 key3 key4 p73 p72 p71 p70 fig. 8 key scan circuit vdd v1 v2 v3 v4 vlcd gnd vdd v1 v2 v3 v4 vlcd gnd 30 s seg com2 fig. 9 key scan signal EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 12 ? bit 1 : zero ? bit 2~4 (bias1~bias3) control bits used to choose lcd operation voltage . lcd operate voltage vop (vdd 5v) vdd=5v 000 0.60vdd 3.0v 001 0.66vdd 3.3v 010 0.74vdd 3.7v 011 0.82vdd 4.0v 100 0.87vdd 4.4v 101 0.93vdd 4.7v 110 0.96vdd 4.8v 111 1.00vdd 5.0v ? bit5:port6 switch , 0/1= normal i/o port/common output ? bit6:port9 low nibble switch , 0/1= normal i/o port/segment output . bit7:port9 high nibble switch page1 : 7654321 0 op77 op76 c2s c1s psc1 psc0 - - ? bit0: unused, please set to 0 ? bit1: unused, please set to 0 ? bit3~bit2: counter1 prescaler , reset=(0,0) (psc1,psc0) = (0,0)=>1:1 , (0,1)=>1:2 , (1,0)=>1:4 , (1,1)=>1:8 ? bit4 :counter1 source , (0/1)=(32768hz/3.679mhz if enable) ? bit5:counter2 source , (0/1)=(32768hz/3.679mhz if enable) scale=1:1 ? bit6:p76 opendrain control (0/1)=(disable/enable) ? bit7:p77 opendrain control (0/1)=(disable/enable) 9. iocf (interrupt mask register) 7654321 0 int3 - c8_2 c8_1 int2 int1 int0 tcif ? bit 0 ~ 7 interrupt enable bit. 0: disable interrupt 1: enable interrupt ? iocf register is readable and writable. it is very important to save acc,r3 and r5 when processing a interruption. address instruction note 0x08 disi ;disable interrupt 0x09 mov a_buffer,a ;save acc 0x0a swap a_buffer 0x0b swapa 0x03 ;save r3 status 0x0c mov r3_buffer,a 0x0d mov a,0x05 ;save rom page register 0x0e mov r5_buffer,a :: :: : mov a,r5_buffer ;return r5 : mov 0x05,a : swapa r3_buffer ;return r3 : mov 0x03,a : swapa a_buffer ;return acc : reti * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 13 vii.3 tcc/wdt prescaler there is an 8-bit counter available as prescaler for the tcc or wdt. the prescaler is available for the tcc only or wdt only at the same time. ? an 8 bit counter is available for tcc or wdt determined by the status of the bit 3 (pab) of the cont register. ? see the prescaler ratio in cont register. ? fig. 10 depicts the circuit diagram of tcc/wdt. ? both tcc and prescaler will be cleared by instructions which write to tcc each time. ? the prescaler will be cleared by the wdtc and slep instructions, when assigned to wdt mode. ? the prescaler will not be cleared by slep instructions, when assigned to tcc mode. wdte wdt timeout pab pab mux 8-to-1 mux psr0~psr2 8-bit counter m u x 0 1 wdt pab tcc overflow interrupt data bus tcc(r1) sync 2 cycle m u x m u x 1 0 0 1 te ts tcc (32k clk) clk(=fosc/2) fig. 10 block diagram of tcc wdt vii.4 i/o ports the i/o registers, port 6 ~ port 9, are bi-directional tri-state i/o ports. port 7 can be pulled-high internally by software control. the i/o ports can be defined as input or output pins by the i/o control registers (ioc6 ~ ioc9 ) under program control. the i/o registers and i/o control registers are both readable and writable. the i/o interface circuit is shown in fig. 11. EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 14 fig. 11 the circuit of i/o port and i/o control register vii.5 reset and wake-up the reset can be caused by (1) power on reset, or voltage detector (2) wdt timeout. (if enabled and in green or normal mode) note that only power on reset, or only voltage detector in case(1) is enabled in the system by code option bit. if voltage detector is disabled, power on reset is selected in case (1). refer to fig. 12. v dd dq clk clr clk reset 18 ms wdt oscillator m u x 1 0 power-on reset voltage detector /enable code option wdte wdt timeout fig. 12 block diagram of reset of controller pcrd d q q clk cl pr d q q clk cl pr pdwr pdrd pcwr m u x 0 1 port iod * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 15 once the reset occurs, the following functions are performed. ? the oscillator is running, or will be started. ? the program counter (r2) is set to all 0. ? when power on, the upper 3 bits of r3 and the upper 2 bits of r4 are cleared. ? the watchdog timer and prescaler are cleared. ? the watchdog timer is disabled. ? the cont register is set to all 1 ? the other register (bit7..bit0) r5 = 00000000 r6 = port ioc6 = 11111111 r7 = port ioc7 = 11111111 r8 = port ioc8 = 11111111 r9 = port ioc9 = 11111111 ra = 010x0xxx ioca = 00000000 rb = 11111111 page0 iocb = 00000000 page1 iocb = 00000000 rc = 00000000 page0 iocc = 0xxxxxxx page1 iocc = 00000000 rd = xxxxxxxx page0 iocd = 00000000 re = 00000000 page0 ioce = 00000000 page1 ioce = 00000000 rf = 00000000 iocf = 00000000 the controller can be awakened from sleep mode or idle mode (execution of slep instruction, named as sleep mode or idle mode) by (1)tcc time out (idle mode only) (2) wdt time-out (if enabled) or, (3) external input at port9 . the three cases will cause the controller wake up and run from next instruction in idle mode , reset in sleep mode . after wake-up , user should control watch dog in case of reset in green mode or normal mode. the last two should be open re register before into sleep mode or idle mode. the first one case will set a flag in rf bit0 . and it will go to address 0x08 when tcc generate a interrupt . vii.6 interrupt the chip has internal interrupts which are falling edge triggered, as followed : tcc timer overflow interrupt (internal) , two 8-bit counters overflow interrupt . if these interrupt sources change signal from high to low , then rf register will generate 1 flag to corresponding register if you enable iocf register. rf is the interrupt status register which records the interrupt request in flag bit. iocf is the interrupt mask register. global interrupt is enabled by eni instruction and is disabled by disi instruction. when one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008h. once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the rf register. the interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. there are four external interrupt pins including int0 , int1 , int2 , int3 . and four internal counter interrupt available. external interrupt int0 , int1 , int2 , int3 signals are from port7 bit0 to bit3 . if iocf is enable then these signal will cause interrupt , or these signals will be treated as general input data . after reset, the next instruction will be fetched from address 000h and the instruction inturrept is 001h and the hardware inturrept is 008h. tcc will go to address 0x08 in green mode or normal mode after time out. and it will run next instruction from slep instruction and then go to address 0x08 in idle mode . these three cases will set a rf flag. EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 16 it is very important to save acc,r3 and r5 when processing a interruption. address instruction note 0x08 disi ;disable interrupt 0x09 mov a_buffer,a ;save acc 0x0a swap a_buffer 0x0b swapa 0x03 ;save r3 status 0x0c mov r3_buffer,a 0x0d mov a,0x05 ;save rom page register 0x0e mov r5_buffer,a :: :: : mov a,r5_buffer ;return r5 : mov 0x05,a : swapa r3_buffer ;return r3 : mov 0x03,a : swapa a_buffer ;return acc : reti vii.7 instruction set instruction set has the following features: (1) every bit of any register can be set, cleared, or tested directly. (2) the i/o register can be regarded as general register. that is, the same instruction can operates on i/o register. the symbol r represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. bits 6 and 7 in r4 determine the selected register bank. b represents a bit field designator which selects the number of the bit, located in the register r, affected by the operation. k represents an 8 or 10-bit constant or literal value. instruction status binary hex mnemonic operation affected 0 0000 0000 0000 0000 nop no operation none 0 0000 0000 0001 0001 daa decimal adjust a c 0 0000 0000 0010 0002 contw a ? cont none 0 0000 0000 0011 0003 slep 0 ? wdt, stop oscillator t,p 0 0000 0000 0100 0004 wdtc 0 ? wdt t,p 0 0000 0000 rrrr 000r iow r a ? iocr none * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 17 instruction status binary hex mnemonic operation affected 0 0001 00rr rrrr 01rr sub a,r r-a ? a z,c,dc 0 0001 01rr rrrr 01rr sub r,a r-a ? r z,c,dc 0 0001 10rr rrrr 01rr deca r r-1 ? az 0 0001 11rr rrrr 01rr dec r r-1 ? rz 0 0010 00rr rrrr 02rr or a,r a v vr ? az 0 0010 01rr rrrr 02rr or r,a a v vr ? rz 0 0010 10rr rrrr 02rr and a,r a & r ? az 0 0010 11rr rrrr 02rr and r,a a & r ? rz 0 0011 00rr rrrr 03rr xor a,r a ? r ? az 0 0011 01rr rrrr 03rr xor r,a a ? r ? rz 0 0011 10rr rrrr 03rr add a,r a + r ? a z,c,dc 0 0011 11rr rrrr 03rr add r,a a + r ? r z,c,dc 0 0100 00rr rrrr 04rr mov a,r r ? az 0 0100 01rr rrrr 04rr mov r,r r ? rz 0 0100 10rr rrrr 04rr coma r /r ? az 0 0100 11rr rrrr 04rr com r /r ? rz 0 0101 00rr rrrr 05rr inca r r+1 ? az 0 0101 01rr rrrr 05rr inc r r+1 ? rz 0 0101 10rr rrrr 05rr djza r r-1 ? a, skip if zero none 0 0101 11rr rrrr 05rr djz r r-1 ? r, skip if zero none 0 0110 00rr rrrr 06rr rrca r r(n) ? a(n-1) r(0) ? c, c ? a(7) c 0 0110 01rr rrrr 06rr rrc r r(n) ? r(n-1) r(0) ? c, c ? r(7) c 0 0110 10rr rrrr 06rr rlca r r(n) ? a(n+1) r(7) ? c, c ? a(0) c 0 0110 11rr rrrr 06rr rlc r r(n) ? r(n+1) r(7) ? c, c ? r(0) c 0 0111 00rr rrrr 07rr swapa r r(0-3) ? a(4-7) r(4-7) ? a(0-3) none 0 0111 01rr rrrr 07rr swap r r(0-3) ? r(4-7) none 0 0111 10rr rrrr 07rr jza r r+1 ? a, skip if zero none 0 0111 11rr rrrr 07rr jz r r+1 ? r, skip if zero none 0 100b bbrr rrrr 0xxx bc r,b 0 ? r(b) none EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 18 vii.8 code option register the chip has one code option register which is not part of the normal program memory. the option bits cannot be accessed during normal program execution. 7654321 0 - - - - - - /povd - ? bit 0 : unsed ? bit 1 ( /povd ) : power on voltage detector. 0 : enable 1 : disable /povd 1.8v reset power on 3.6v detect no 3.6v detect control sleep mode reset reset by ra(5) current 1 no yes yes yes 1 m a 0 yes yes yes yes 15 m a ? bit 2~7 : unused, must be "0"s. vii.9 lcd driver the chip can drive lcd directly and has 60 segments and 16 commons that can drive 60*16 dots totally. lcd block is made up of lcd driver , display ram, segment output pins , common output pins and lcd operating power supply pins. duty , bias , the number of segment , the number of common and frame frequency are determined by lcd mode register . lcd control register. the basic structure contains a timing control which uses the basic frequency 32.768khz to generate the proper timing for different duty and display access. re register is a command register for lcd driver, the lcd display ( disable, enable, blanking) is controlled by lcd_c and the driving duty and bias is decided by lcd_m and the display data is stored in data ram which address and data access controlled by registers iocb and iocc. lcd timing control re(lcd_c,lcd_m) bias control vdd-vlcd lcd duty control lcd commom control com ram iocb iocc display data control lcd segment control seg 32.768khz fig. 13 lcd driver control * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 19 1. lcd driver control re(lcd driver control)(initial state 00000000) 7654321 0 - - - - - lcd_c2 lcd_c1 lcd_m ? bit0 (lcd_m):lcd_m decides the methods, including duty, bias, and frame frequency. ? bit1~bit2 (lcd_c#):lcd_c# decides the lcd display enable or blanking. change the display duty must set the lcd_c to 00. lcd_c2,lcd_c1 lcd display control lcd_m duty bias 0 0 change duty 0 1/16 1/4 disable(turn off lcd) 1 1/8 1/4 0 1 blanking : : 1 1 lcd display enable : : 2. lcd display area the lcd display data is stored in the data ram . the relation of data area and com/seg pin is as below: com15 ~ com8 com7 ~ com0 40h (bit15 ~ bit8) 00h (bit7 ~ bit0) seg0 41h 01h seg1 :: : :: : 7bh 3bh seg59 7ch 3ch empty 7dh 3dh empty 7eh 3eh empty 7fh 3fh empty ? iocb(lcd display ram address) 7654321 0 - lcda6 lcda5 lcda4 lcda3 lcda2 lcda1 lcda0 bit 0 ~ bit 6 select lcd display ram address up to 120. lcd ram can be write whether in enable or disable mode and read only in disable mode. ? iocc(lcd display data) : bit 0 ~ bit 8 are lcd data. 3. lcd com and seg signal ? com signal : the number of com pins varies according to the duty cycle used, as following: in 1/8 duty mode com8 ~ com15 must be open. in 1/16 duty mode com0 ~ com15 pins must be used. EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 20 com0 com1 com2 com3 com4 com5 com6 com7 com8 .. com15 1/8o o oo oooox ..x 1/16 o o o o o o o o o .. o x:open,o:select ? seg signal: the 60 segment signal pins are connected to the corresponding display ram address 00h to 3bh. the high byte and the low byte bit7 down to bit0 are correlated to com15 to com0 respectively. when a bit of display ram is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select signal is sent to the corresponding segment pin. ? com, seg and select/non-select signal is shown as following: vdd v1 v2 v3 vlcd vdd v1 v2 v3 vlcd com1 com0 com0 ... com7 frame vdd v1 v2 v3 vlcd com2 vdd v1 v2 v3 vlcd seg vdd v1 v2 v3 vlcd seg dark light fig. 14 lcd wave 1/4 bias, 1/8 duty * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 21 fig. 15 lcd wave 1/4 bias, 1/16 duty EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 22 4. lcd bias control ioce (bias control register) 7654321 0 bias3 bias2 bias1 bit 2~4 (bias1~bias3) control bits used to choose lcd operation voltage . lcd operate voltage vop (vdd 5v) vdd=5v 000 0.60 v dd 3.0 v 001 0.66 v dd 3.3 v 010 0.74 v dd 3.7 v 011 0.82 v dd 4.0 v 100 0.87 v dd 4.4 v 101 0.93 v dd 4.7 v 110 0.96 v dd 4.8 v 111 1.00 v dd 5.0 v ? bit 5~7 unused fig. 16 lcd bias circuit * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 23 ix. dc electrical characteristics (t a = 0 c~70 c, v dd = 5v 5%; v ss = 0v) parameter sym. condition min. typ. max. unit input leakage current i il1 v in = v dd , v ss 1 m a for input pins input leakage current i il2 v in = v dd , v ss 1 m a for bi-directional pins input high voltage v ih 2.5 v input low voltage v il 0.8 v input high threshold v iht /reset, tcc, rdet1 2.0 v voltage input low threshold v ilt /reset, tcc, rdet1 0.8 v voltage clock input high voltage v ihx osci 3.5 v clock input low voltage v ilx osci 1.5 v key scan input high voltage vhscan port6 for key scan 3.5 v key scan input low voltage vlscan port6 for key scan 1.5 v output high voltage v oh1 i oh = 1.6 ma 2.4 v (port5,6,7,8) (port9) i oh = 6 ma 2.4 v output low voltage v ol1 i ol = 1.6 ma 0.4 v (port5,6,7,8) (port9) i ol = 6 ma 0.4 v com voltage drop v com i o = 50 m a - - 2.9 v segment voltage drop v seg i o = 50 m a - - 3.8 v lcd drive reference v lcd contrast adjustment voltage pull-high current i ph pull-high active input pin at v ss -50 -100 -240 m a power down current i sb1 all input and i/o pin at v dd ,1 m a output pin floating, wdt disabled idle mode current i sb-1 all input and i/o pin at v dd , output pin 15 m a floating, wdt disabled,lcd enable low clock current i sb2 clk=32.768 khz, all input and i/o pin 50 m a at v dd , output pin floating, wdt disabled, lcd enable operating supply current i cc /reset=high, clk=3.679mhz, output pin 1.2 ma floating rating sym. value unit dc supply voltage v dd -0.3 to 6 v input voltage v in -0.5 to v dd +0.5 v operating temperature range t a 0 to 70 c viii. absolute maximum ratings EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 24 x. ac electrical characteristic ( t a = 0 ~ 70 c, v dd = 5v,v ss = 0v ) parameter sym. condition min. typ. max. unit input clk duty cycle dclk 45 50 55 % instruction cycle time tins 32.768k 60 m s 3.679m 550 m s device delay hold time tdrh 18 ms tcc input period ttcc note 1 (tin+20)/n ns watchdog timer period twdt t a = 25 c18ms note 1: n = selected prescaler ratio. * this specification is subject to be changed without notice. 4.17.2000 EM78P860 8 -bit micro-controller 25 xi. timing diagrams fig. 17 ac timing 2.4 0.45 2.0 0.8 2.0 0.8 clk nop tdrh instruction 1 executed tcc tins ttcc reset timing (clk="0") tcc input timing (clk="0") ac test input/output waveform ac testing : input is driven at 2.4v for logic "1", and 0.45v for logic "0". timing measurements are made at 2.0v for logic "1", and 0.8v for logic "0". test ponits clk /reset EM78P860 8 -bit micro-controller * this specification is subject to be changed without notice. 4.17.2000 26 xii. application circuit emc78860 lcd i/o common segment vdd lobat /reset test gnd xin xout pllc battery detector cd power supply power on reset 30p 0.01 30p 32768 keypad EM78P860 fig. 18 application circuit for data bank |
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